I see that you have the datain bus connected to slide switches and the dataout bus connected to the LEDs.

I assume that the board has a fixed clock and that it is indeed at location C9 Also, are you sure you have the right polarity on the rstwrrd signals.

The one thing that I did add is an edge detect for the rd and wr signals.

On my board the switch inputs are always high (pull-up resistors) and only go low when the switch is depressed.

Since a press of the switch creates a logic low condition I had to invert the rdwr signals to get them to work correctly with your code.

Trying to get something working on the actual hardware can be daunting the first time since there are some many places things can go wrong.

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Fifo Verilog Code Basic